Integrated enhancement mode and depletion mode device structure and method of making the same

US10854600B2 · kind B2 · utility

Assignee

• NORTHROP GRUMMAN SYSTEMS CORPORATION · US

Inventors

• Justin Andrew Parke · Ellicott City, US
• Eric J. Stewart · Silver Spring, US
• Robert S. Howell · Silver Spring, US
• Howell George Henry · Ellicott City, US
• Bettina Nechay · Laurel, US
• Harlan Carl Cramer · Columbia, US
• Matthew Russell King · Wake Forest, US
• Shalini Gupta · Baltimore, US
• Ronald G. Freitag · Ellicott City, US
• Karen Marie Renaldo · Pasadena, US

Key dates

• Filing date: Sep 20, 2019
• Grant date: Dec 1, 2020
• Expiry date: Sep 20, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.