Multi-level turn-off circuit and related methods
US10855275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.