Parallelized successive interference cancellation (PSiC) receiver architecture for wireless communications systems
US10855327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Mar 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/71075
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The disclosed systems, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a signal encoding module to encode a plurality of received analog signals with an orthogonal code set and combine the encoded analog signals into a single encoded analog composite signal, an analog-to-digital conversion unit to convert the single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals. The presented configurations also include a bank of multiple successive interference cancellation (SiC) modules to sequentially remove the constituent digital signals from the single encoded digital composite signal until a single constituent digital signal remains and a decoding module configured to decode the remaining constituent digital signal from the single encoded digital composite signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.