Efficient signaling scheme for high-speed ultra short reach interfaces
US10855498B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2017 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Mar 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device includes a substrate and first, second, and third integrated circuit (IC) chips. The first integrated circuit (IC) chip is mounted on the substrate to receive first data and includes a first transfer interface to transmit the first data via first conductors formed in the substrate. The second IC chip mounts on the substrate and has a second transfer interface to receive the first data. The second IC includes on-chip conductors to route the first data on-chip to an output interface. The output interface transmits the first data via second conductors formed on the substrate. A third IC chip mounts on the substrate and has a third transfer interface to receive the first data via the second conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.