Storage circuitry responsive to a tag-matching command
US10860495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2017 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Sep 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.