Systems and methods for enhanced clock tree power estimation at register transfer level
US10860761B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Jun 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example systems and methods are disclosed for estimating power consumption by a clock tree in a register-transfer level (RTL) circuit design based on a previously generated reference gate-level circuit design. A plurality of regions within the clock tree structure of the reference gate-level circuit design are identified, where the plurality of regions are demarcated by one or more clock gating structures. A region-based clock model is generated that includes at least one clock constraint model for each identified region. The region-based clock model is used to synthesize the clock tree in the RTL circuit design for estimating power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.