Method and system for fabricating integrated circuit with aid of programmable circuit synthesis
US10860777B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Jun 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/373
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure is provided. The method includes assigning a set of parameter values to a set of size parameters of a unit cell of the integrated circuit in a unit cell schematic of the unit cell according to a predetermined criterion, wherein the unit cell characterized by the set of parameter values has a circuit characteristic meeting the predetermined criterion; generating a unit cell layout of the unit cell according to the unit cell schematic; generating a circuit layout comprising a plurality of replicas of the unit cell layout, the replicas of the unit cell layout being arranged in correspondence with circuit blocks in a circuit floorplan of the integrated circuit, respectively; and fabricating the integrated circuit according to the circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.