Three-dimensional semiconductor memory device
US10861863B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Dec 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device includes a horizontal semiconductor layer provided on a lower insulating layer. The horizontal semiconductor layer includes a cell array region and a connection region. An electrode structure is provided including electrodes. The electrodes are stacked on the horizontal semiconductor layer. The electrodes have a staircase structure on the connection region. A plurality of first vertical structures are provided on the cell array region to penetrate the electrode structure. A plurality of second vertical structures are provided on the connection region to penetrate the electrode structure and the horizontal semiconductor layer. Bottom surfaces of the second vertical structures are positioned at a level lower than a bottom surface of the horizontal semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.