Low power cycle to cycle bit transfer in gate drivers
US10862483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Jan 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate driver includes a high-side region that operates in a first voltage domain, a low-side region that operations in a second voltage domain lower than the first voltage domain, a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain, a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, where each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.