Techniques to improve linearity of R-2R ladder digital-to-analog converters (DACs)
US10862493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Apr 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.