Background offset drift calibration circuit and method for comparator
US10862494B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A background offset drift calibration circuit and method for comparator are proposed. The background calibration circuit and method are designed based on the approximate linear characteristic of the offset drift of a comparator caused by the variation of temperature and power supply. The calibration circuit for the comparators obtains the offset drift characteristic of each comparator by performing twice foreground calibration and selects the comparator with the largest drift as the reference comparator and other comparators as working comparators. The reference comparator is configured to track the offset drift and trigger the background calibration circuit of other working comparators. The working comparators compensate for the offset drift caused by the temperature or the power supply in the background by linear interpolation based on the offset drift characteristic of each comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.