Digital interpolation of switch point to reduce switch point jitter
US10866288B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Jun 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A sensor is provided to include: a sampling clock circuit generating a sample clock signal with a predetermined sample clock period; a system clock circuit generating a system clock signal with a predetermined system clock period, wherein a value of the system clock period is less than a value of the sample clock period; a sensor circuit generating, during each sample clock period, a sensor signal representing a position of an object; a sampling circuit receiving the sensor signal and generate sample signal value in response; an interpolation circuit determining a first difference between a current sample signal and a previous sample signal, determining a second difference between a switchpoint threshold value and the previous sample signal, and determining a delay count based upon a ratio of the first difference and the second difference; and a switchpoint signal circuit generating a switchpoint signal based upon the delay count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.