Device integrated with depletion-mode junction fielf-effect transistor and method for manufacturing the same
US10867995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2017 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Sep 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/82
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.