Semiconductor structure and method
US10868106B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | May 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1206
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.