Semiconductor circuit and semiconductor circuit layout system
US10868524B2 · kind B2 · utility
1Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Aug 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit and a semiconductor circuit layout system are provided. The semiconductor circuit includes a clock inverter which inverts a clock signal and outputs an inverted clock signal where the clock inverter is laid out between a second master latch main circuit configured to latch signals of a first node and a fourth node based on the clock signal and the inverted clock signal, respectively, and a second slave latch main circuit configured to latch signals of a second node and a fifth node based on the clock signal and the inverted clock signal, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.