Code generator including asynchronous counter and synchronous counter, and operating method thereof
US10868541B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Nov 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/616
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.