Frequency divider circuit, demultiplexer circuit, and semiconductor integrated circuit
US10868552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Sep 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.