Digital resolution enhancement for high speed digital-to-analog converters
US10868561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2018 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Nov 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0425
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method for increasing the effective resolution of digital-to-analog conversion for the purpose of digital pre-distortion to compensate distortions of a communication channel, according to which a digital sequence of N samples x(n) to be transmitted over the communication channel are received and several quantization possibilities are generated by performing Soft Quantization (SQ) on each sample, using a soft quantizer, where low computational complexity is maintained by limiting the number of SQ possibilities. The Instantaneous costs for each possible SQ error is computed and converging paths in the Trellis diagram, which represents possible states and transitions between them, for each sample is eliminated. Then the averaged errors for each remaining path are computed and Hard-Quantization is performed to eliminate converging paths and to keep a constant number of states. These steps are repeated N times, one time for each sample and the optimal path with the lowest averaged error selecting. Then the sequence associated with the optimal path is fed into the DAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.