Frequency independence for synthesis within programmable non-reciprocal network circuit
US10868576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Apr 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus includes parallel delay lines, each exhibiting a delay; a first set of switches for each port of a first set of ports, each of which is to selectively couple a port of the first set of ports to first ends of the delay lines; a second set of switches for each port of a second set of ports, each of which to selectively couple a port of the second set of ports to second ends of the delay lines. A signal source generates a series of clock signals that are sequentially time delayed between the first set of switches and the second set of switches, where an input signal at one of the first or second sets of ports travels from the one of the first or second sets of ports to an output port of opposite set of ports over the delay lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.