Periphery shoreline augmentation for integrated circuits
US10871906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Jan 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.