Architecture for sparse neural network acceleration
US10871964B2 · kind B2 · utility
1Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Aug 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, a computer-readable medium, and an apparatus for a sparse neural network are provided. The apparatus may include a hardware accelerator. The apparatus may determine, for each pair of operands to be processed by a MAR unit, whether both operands of the pair are non-zero. The apparatus may prevent a pair of operands to be processed by the MAR unit from being loaded to a multiplier of the MAR unit when an operand of the pair of operands is zero. The apparatus may place the pair of operands into one of a plurality of queues when both operands of the pair of operands are non-zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.