Neural network processor with direct memory access and hardware acceleration circuits
US10872290B2 · kind B2 · utility
2Cited by
39References
20Claims
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Key dates
| Filing date | Sep 21, 2017 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Jun 12, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamically adaptive neural network processing system includes memory to store instructions representing a neural network in contiguous blocks, hardware acceleration (HA) circuitry to execute the neural network, direct memory access (DMA) circuitry to transfer the instructions from the contiguous blocks of the memory to the HA circuitry, and a central processing unit (CPU) to dynamically modify a linked list representing the neural network during execution of the neural network by the HA circuitry to perform machine learning, and to generate the instructions in the contiguous blocks of the memory based on the linked list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.