Systems and methods for calibrating impedance of a low power voltage-mode transmitter driver
US10873323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2020 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-power transmitter for transmitting digital signals from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver comprised of a plurality of driver slices, which includes an up-cell having a first resistor and a first transistor, and a down-cell having a second resistor, a second transistor, and a third transistor. A calibration circuit drives a replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the up-cell and adjusting a second gate voltage applied to the third transistor of the replica of the down-cell. The calibrated first gate voltage is applied to the first transistor and to the second transistor of each of the plurality of driver slices and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.