Patent · US Active

Spur frequency estimation inside digital phase locked loop

US10873333B2 · kind B2 · utility

2Cited by

5References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Rotem Avivi · Petah Tikva, IL
Michael Kerner · Netanya, IL
Yair Dgani · Raanana, IL

Key dates

Filing date	May 31, 2017
Grant date	Dec 22, 2020
Priority date	—
Expiry date	May 31, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.