Divider control and reset for phase-locked loops
US10873335B2 · kind B2 · utility
2Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | May 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.