Generating lower frequency multi-phase clocks using single high-frequency multi-phase divider
US10873443B1 · kind B1 · utility
1Cited by
9References
17Claims
0Family size
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Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.