Low latency video codec and transmission with parallel processing
US10873754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2018 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Dec 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/176
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.