Context switches with processor performance states
US10877548B2 · kind B2 · utility
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Key dates
| Filing date | Mar 9, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Nov 11, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In example implementations, an apparatus is provided. The apparatus includes a context switch block, a processor performance state block, and a task execution block. The context switch block is to perform a context switch. The processor performance state block is to load a processor with a processor performance state stored in a context information associated with a task. The task execution block is to execute the task with the processor operating at the processor performance state loaded from the context information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.