Processing vectorized guest physical address translation instructions
US10877788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Mar 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples include a processor including fetch circuitry to fetch a guest physical address translation instruction having a format with fields to specify at least an opcode and locations of a source vector and a destination vector, decode circuitry to decode the fetched guest physical address translation instruction, and execution circuitry to execute the decoded guest physical address translation instruction. Execution of the decoded guest physical address translation instruction includes comparing guest physical addresses of the source vector with base and end addresses of a selected memory region, masking a guest physical address of the source vector if the guest physical address is in the selected memory region, translating the masked guest physical addresses into host addresses, and storing the host addresses into the destination vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.