Scheduler for vector processing operator allocation
US10877811B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a scheduler circuit and an operator allocation circuit. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more operators, (ii) track a plurality of first status signals indicating a readiness state of a plurality of unscheduled operators that are to be allocated to a plurality of hardware engines, (iii) track a plurality of second status signals indicating a readiness state of the hardware engines, and (iv) for each operator, track a resource type parameter. The operator allocation circuit may be configured to (a) select a resource type from a list of resource types in use, (b) determine available hardware engines corresponding to the selected resource type based on the second status signals, (c) generate scores for the unscheduled operators based on (i) the selected resource type, (ii) the first status signals, and (iii) the resource type parameters, and (d) allocate at least one of the unscheduled operators to at least one of the available hardware engines based on the scores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.