Hardware environment and method of performing matrix multiplication in artificial intelligence applications
US10877812B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 6, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Jan 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of hardware accelerators are interconnected and include a special processing unit and accelerator memory. At least one host computer is coupled to each of the plurality of hardware accelerators and includes a general processing unit and host memory. The plurality of hardware accelerators exchange data in a ring communication pattern in computing a linear layer of a neural network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.