Array substrate
US10878764B2 · kind B2 · utility
1Cited by
0References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Sep 18, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0223
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.