Latch-up prevention circuit for memory storage system
US10878852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Nov 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storage systems selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storage systems selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the configurable memory storage systems selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors. In some situations, the configurable memory storage systems can dynamically adjust the maximum operational voltage signal to compensate for fluctuations in the maximum operational voltage signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.