Self aligned via and method for fabricating the same
US10879120B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 2, 2017 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02178
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.