Enhancement mode saddle gate device

US10879382B1 · kind B1 · utility

Assignee

• NORTHROP GRUMMAN SYSTEMS CORPORATION · US

Inventors

• Josephine B. Chang · Mahopac, US
• Ken Alfred Nagamatsu · Ellicott City, US
• Robert S. Howell · Silver Spring, US
• Sarat Saluru · Baltimore, US

Key dates

• Filing date: Jun 26, 2019
• Grant date: Dec 29, 2020
• Expiry date: Jun 26, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0254
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An enhancement-mode (e-mode) field effect transistor (FET) comprises a buffer layer, and a superlattice of conducting channels on the buffer layer and including a trench that cuts down through the superlattice into the buffer layer and separates the superlattice into a source-access region and a drain-access region, wherein the buffer layer forms a bottom of the trench. The e-mode FET includes a source and a drain adjacent to the source-access region and the drain-access region, respectively. The e-mode FET further includes a gate in the trench, such that a voltage above a threshold voltage of the e-mode FET applied to the gate induces a current channel in the buffer layer underneath the gate, which electrically connects the source-access region to the drain-access region to turn on the e-mode FET, and (ii) a voltage below the threshold voltage applied to the gate eliminates the current channel, which electrically disconnects the source-access region from the drain-access region to turn off the e-mode FET.