Low-power fast-setting delay circuit
US10879882B1 · kind B1 · utility
2Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a delay circuit includes a delay line including a bias input. The delay circuit also includes a bias generator including a clock input, and a bias output, wherein the bias output of the bias generator is coupled to the bias input of the delay line. The delay circuit further includes a multiplexer including a first input, a second input, and an output, wherein the first input of the multiplexer is configured to receive a first clock signal, the second input of the multiplexer is configured to receive a second clock signal, and the output of the multiplexer is coupled to the clock input of the bias generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.