Through silicon interposer wafer and method of manufacturing the same
US10882737B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Mar 23, 2017 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49827
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through silicon interposer wafer and method of manufacturing the same. A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.