Computing device within memory processing and narrow data ports
US10884657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2016 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Oct 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.