Fault tolerant memory system
US10884850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2018 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Dec 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.