Cache allocation for controller boards based on prior input-output operations
US10884935B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Sep 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A metadata structure of a storage array stores metadata associated with a plurality of prior input-output operations. The metadata comprises an indication of which of the controller boards was utilized to service a prior input-output operation and an input-output size for the prior input-output operation. A given input-output operation is obtained and a target controller board and a target portion of the storage array are identified based at least in part on the given input-output operation. A given controller board is determined to have a higher likelihood of receiving a future input-output operation than at least one other controller board based at least in part on the metadata and a portion of the cache is allocated to the given controller board for storing target data associated with the given input-output operation. The target controller board utilizes the portion of the cache allocated to the given controller board to service the input-output operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.