Memory devices comprising a write assist circuit
US10885954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2017 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Sep 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.