Method and circuit for protecting a DRAM memory device from the row hammer effect
US10885966B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2020 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Aug 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.