Semiconductor memory device and control method therefor
US10885982B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Jul 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell including a first memory unit and a second memory unit which are coupled to a complementary bit line pair, an operation controller configured to successively select the first memory unit and the second memory unit, during a read operation which reads data from the memory cell, a first readout unit coupled to one of the bit line pair, and configured to judge a logical value of the data read from the selected first memory unit onto the one of the bit line pair, and a second readout unit coupled to the other of the bit line pair, and configured to judge a logical value of the data read from the selected second memory unit onto the other of the bit line pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.