Compact antifuse element and fabrication process
US10886283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Jul 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes at least one antifuse element. The antifuse element is formed from a semiconductor substrate, a trench extending down from a first face of the semiconductor substrate into the semiconductor substrate, a first conductive layer housed in the trench and extending down from the first face of the semiconductor substrate into the semiconductor substrate, a dielectric layer on the first face of the semiconductor substrate, and a second conductive layer on the dielectric layer. A program transistor selectively electrically couples the second conductive layer to a program voltage in response to a program signal. A program/read transistor selectively electrically couples the first conductive layer to a ground voltage in response to the program signal and in response to a read signal. A read transistor selectively electrically couples the second conductive layer to a read amplifier in response to the read signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.