Display device having stress buffer layered vias
US10886482B2 · kind B2 · utility
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20References
16Claims
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Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Jun 26, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A flexible display panel, a manufacturing method thereof and a display device are provided. The flexible display panel includes: a flexible substrate, a first metal layer formed on the substrate, an insulation layer overlying the first metal layer, and a second metal layer disposed on the insulation layer, wherein a plurality of via holes are provided in the insulation layer, the inner wall of each via hole is covered by a stress buffer layer and the second metal layer is formed on the stress buffer layer and connected to the first metal layer through the via holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.