Circuitry for low input charge analog to digital conversion
US10886931B1 · kind B1 · utility
1Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Jul 24, 2020 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Jul 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes analog input nodes and switches selectively coupling each of the analog input nodes to a capacitive node. Each of the switches is controlled by a respective bit of a channel selection word. Level shifting circuits are respectively coupled in parallel with the switches. A sampling capacitor is coupled between an output node and ground, the output node being coupled to the capacitive node. An analog to digital converter operates to digitize voltages at the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.