Patent · US Active

On-chip execution of in-system test utilizing a generalized test image

US10890620B2 · kind B2 · utility

0Cited by
7References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 17, 2019
Grant dateJan 12, 2021
Priority date
Expiry dateMay 17, 2039

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318566
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.