On-chip execution of in-system test utilizing a generalized test image
US10890620B2 · kind B2 · utility
0Cited by
7References
18Claims
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Key dates
| Filing date | May 17, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | May 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.