Hardware, software and algorithm to precisely predict performance of SoC when a processor and other masters access single-port memory simultaneously
US10891071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2018 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Apr 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, program control code, and hardware circuit are provided for predicting performance of an system-on-chip (SoC) (100) having a processor (105) and a master device (106) having shared access to a single-port memory (104) by activating a timer (102) in a Performance Monitoring Unit (PMU) (101) to measure a specified number of cycles of the processor in a defined measure instance and by activating a memory access counter (103) in the PMU to measure a first count of memory access requests to the single-port memory by the processor in the defined measure instance and to measure a second count of memory access requests to the single-port memory by the master device in the defined measure instance, so that the first and second counts are stored in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.