Flash memory and operation method thereof
US10891190B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a nonvolatile memory and an operation method thereof. The nonvolatile memory includes a memory cell array and a controller. The controller is configured to: read out raw data from a plurality of memory cells in the memory cell array; correct the raw data by using error correction code (ECC) data to obtain corrected data; determine an address of a memory cell having a data loss error in the plurality of memory cells; and program the memory cell having the data loss error. After the ECC correction in the read operation, the data loss error is corrected by a program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.