Heterogeneous multiprocessor including scalar and SIMD processors in a ratio defined by execution time and consumed die area
US10891255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2015 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Oct 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a heterogeneous multicore processor is described that is optimized to execute multi-stage computer vision algorithms such as cascade classifier workloads. In such embodiment the heterogeneous processor includes at least one SIMD core, such as a vector processor core, coupled with one or more scalar cores. In one embodiment the heterogeneous multiprocessor executes multi-stage compute operations, where the SIMD core computes a first set of stages and the one or more scalar cores compute the second set of stages. In one embodiment, a process for designing a heterogeneous multicore processor is disclosed which optimizes the ratio of scalar to SIMD cores based on execution time of the multi-stage compute operation in relation to processor die area consumed by a processor configuration having the ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.